Quasi-accumulation mode FET

ABSTRACT

A Field Effect Transistor (FET) capable of withstanding increased positive gate biasing with respect to the source contact without incurring the penalty of drawing excessive gate current, comprising a semi-insulating substrate layer; an active channel layer of doped n-type semi-conductor material disposed on the substrate layer; a first heteroepitaxial semi-insulating layer of a semi-insulating material having a bandgap greater than the bandgap of the active channel layer material disposed on said active channel layer. The first heteroepitaxial layer has a top surface, a designated first region, a designated second region, and a designated middle section disposed therebetween wherein the first region and the second region of the first heteroepitaxial layer are implanted with activated donor impurities to form its source and drain regions. The device is also provided with conventional source, drain and gate contacts. In a preferred embodiment, a heavily donor doped Gallium arsenide heteroepitaxial layer is disposed between the source contact and the first heteroepitaxial layer and between the drain contact and the first heteroepitaxial layer. In one embodiment, the first heteroepitaxial layer is impurity doped with chromium or vanadium.

BACKGROUND OF THE INVENTION

The present invention relates to semiconductor device technology andmore particularly to Quasi-Accumulation Mode Power Field EffectTransistors (QAMFETs).

The gallium arsenide (GaAs) metal Schottky barrier field effecttransistor (MESFET) has been known since 1964 and is now in widespreaduse. In normal MESFET operation the gate contact is biased negative withrespect to the source contact and electron current flows from a sourceregion to a drain region via an active channel disposed under a gate. Atmaximum negative potential the electrons under the gate are driven(repelled) away from the gate and pinch-off of the flow of electrons(current) from the source to the drain edge of the device occurs. As thenegative gate potential is decreased, electrons flow from the sourcethrough the active channel to the drain edge producing current flow.This is called depletion mode operation. When the gate is biasedpositive with respect to the source in a normal MESFET many of theelectrons from the source edge of the GaAs channel are collected by thegate and current flow from source to drain is reduced. For a given gatevoltage the channel current flow increases as the drain voltageincreases. Eventually, for sufficiently large drain voltages, thecurrent will saturate. Voltage breakdown on the drain edge of thecontrol gate occurs at a larger voltage. Thus a significant limitationof the GaAs MESFET is its inability to handle large voltages withoutexperiencing voltage breakdown on the drain edge of the control gate.Another limitation is the self-depletion of charge carriers just beneaththe upper surface of the active channel as a result of mid-gap Fermilevel pinning associated with large surface state densities of fixedcharge.

To overcome the self-depletion of charge problem, manufacturers of GaAspower MESFETs have generally resorted to the fabrication of activechannel layers much thicker than required for optimum deviceperformance. These channels are then etched back in their centers untilthe saturated source-drain current value is acceptable. A Schottkycontrol gate is then deposited in the etched-back mid channel region.The procedure is known as recessed gate technology and has become theindustry standard. FIG. 1 is a schematic crosssection diagram of a priorart MESFET 10 device manufactured according to this process. The MESFETis provided with an n-Type recessed GaAs Epitaxial channel 12, a sourcecontact 14, a metal gate 16 and a drain contact 18 grown in order on asemi-insulating GaAs substrate 20.

Fabrication by the recessed gate technology is cumbersome and does notlend itself to high yield, integrated circuit fabrication as theetch-back must be carefully done under electrical bias in a wet chemicalsolution. The result is a very non-planar surface.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a fieldeffect transistor capable of withstanding increased positive gatebiasing with respect to the source contact without incurring the penaltyof drawing excessive gate current.

It is yet another object of the present invention to provide a fieldeffect transistor which is not degraded by self-depletion problems.

Yet another object of the present invention is to provide a field effecttransistor which eliminates the need for carefully controlled etchbackunder electrical bias during fabrication.

Yet another object of the present invention is to provide a field effecttransistor with increased voltage handling capabilites compared to priorart transistors.

These and other objects of the present invention are achieved by atransistor which includes a semi-insulating substrate layer; an activechannel layer of doped n-type semiconductor material disposed on theactive channel layer; and a first heteroepitaxial semi-insulating layerof semiconductor material disposed on the active channel layer. Thefirst heteroepitaxial layer material has a bandgap greater than thebandgap of the active channel layer material. The first heteroepitaxiallayer has a top surface, a designated first region, a designated secondregion, and a designated middle section therebetween. The first regionand the second region are implanted with donor impurities and activated.The transistor further includes a source contact disposed on the topsurface of the first region of the first heteroepitaxial layer. A draincontact is also disposed on the top surface of the second region of thefirst heteroepitaxial layer. A gate control contact is also disposed onthe first heteroepitaxial layer positioned on the middle region betweenthe source contact and the drain contact and being physically separatedfrom the source contact and the drain contact.

In a preferred embodiment, a heavily donor-doped gallium arsenideheteroepitaxial layer is disposed between the source contact and thefirst heteroepitaxial layer and between the drain contact and the firstheteroepitaxial layer. In one embodiment, the first heteroepitaxiallayer is impurity doped with chromium or vanadium to improve itsinsulating quality.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectioned diagram of a prior art MESFETdevice.

FIG. 2 is a schematic cross-sectioned diagram of one embodiment of thetransistor of the present invention.

FIG. 3 is a second schematic cross-sectioned diagram of the embodimentof FIG. 2.

FIG. 4 is a graph of drain current vs. drain voltage.

FIG. 5 is a schematic cross-sectioned diagram of a second embodiment ofthe transistor of the present invention showing implanted donorimpurities.

FIG. 6 is a schematic cross-sectioned diagram of a third embodiment ofthe transistor of the present invention showing a second heteroepitaxiallayer disposed between the source contact and the first heteroepitaxiallayer, and a third heteroepitaxial layer disposed between the draincontact and the first heteroepitaxial layer.

FIG. 7 is a graph comparing drain current vs. gate potential of a MESFETand a QAMFET.

FIG. 8 is a graph comparing output power vs. input power of a MESFET anda QAMFET.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to the drawings, wherein like reference charactersdesignate like or corresponding parts throughout the several views, FIG.1 is a schematic cross-sectioned diagram of a prior art MESFET device.The MESFET 10 is provided with an n-type recessed GaAs epitaxial channel12, a source contact 14, a gate contact 16 and a drain contact 18 grownin order on a semi-insulating GaAs substrate 20.

FIG. 2 shows the transistor 22 of the present invention. Transistor 22comprises a semi-insulating substrate layer 24; an active channel layer26 of doped n type semiconductor material disposed on the active channellayer 26; and a first heteroepitaxial semi-insulating layer 28 ofsemiconductor material disposed on the active channel layer 26. Thefirst heteroepitaxial layer material 28 has a band gap greater than theband gap of the active channel layer material 26. The firstheteroepitaxial layer 28 has a top surface 30, a designated first region32, a designated second region 34, and a middle region 36 therebetween.The first side 32 and the second side 34 are implanted with donorimpurities and activated by optical flash to form n+regions 37,38.Control Gate 44 forms the mask for the ion implantation. The transistor22 further includes a source contact 40 disposed on the top surface 30of the first heteroepitaxial layer 28 on the first region of the firstheteroepitaxial layer 28. A drain contact 42 is also disposed on the topsurface 30 on the second region 34 of the first heteroepitaxial layer28. A gate control contact 44 is disposed on the middle region 36 of theheteroepitaxial layer 28 between the source contact 40 and the draincontact 42 and is physically separated from the source contact 40 andthe drain contact 42 by spacings 46,48.

The embodiment of the transistor as shown in FIG. 2 uses asemi-insulating substrate layer 24 of gallium arsenide as a base,however any substrate material capable of insulating the FET activestructure from the remaining components of the transistor may be used.Those substrate materials include semi-insulating gallium aluminumarsenide.

The active channel layer 26 is provided as a path along which themajority carriers flow from the source 40 to the drain contact 42 andmay be fabricated of any material suitable for this purpose. In theembodiment of FIG. 2 n-type gallium arsenide, donor doped to a level of2×10¹⁷ cm⁻³ was used. The thickness and impurity doping are conventionaland are chosen in the usual manner to provide for desired devicecharacteristics. The active channel 26 layer is shown by way of exampleas being 120 nanometers in thickness.

While the material of the first heteroepitaxial layer 28 may take avariety of forms, when the active channel layer 26 is a semi-conductormaterial such as gallium arsenide the heteroepitaxial layer 28 mayconveniently take the form of semi-insulating gallium aluminum arsenide.The heteroepitaxial layer 28 may be deposited over the active channellayer 26 by a variety of techniques. These techniques include molecularbeam epitaxy (MBE) and metal oxide chemical vapor deposition (MOCVD).

The heteroepitaxial layer 28 disposed over the active channel layer 26performs several important features providing for the invention of thepresent application. The layer 28 provides a ready source of electronsfor the active channel and acts as a barrier to retard the flow ofelectrons into the gate contact. Initially the layer 28 should comprisean undoped semi-insulating material having a bandgap greater than thebandgap of the active channel layer 26 material. In the embodiment ofFIG. 2 gallium aluminum arsenide was used. Although virtually any molefraction ratio of gallium aluminum arsenide may be used, bestperformance is achieved by 23% aluminum or 90-100% aluminum. The firstregion 32 and the second region 34 of the heteroepitaxial layer 28beneath the sourc 40 and drain contact 42 are implanted with donorimpurities to form regions 36,38 to improve source and drain ohmiccontact conductivity. These implanted impurities must, of course, beprevented from entering the middle section 36 the GaAlAs layer 28beneath the gate 44. This is best accomplished by using the overhangingmushroom-shaped control gate as an integral mask for the implant. Inthis manner, a self-aligned gate structure is fabricated which, in turn,further reduces ohmic losses. The impurity implant may be byconventional means followed by a 900° C., 8 second quartz-IR anneal orit may be by ion beam mixing. The preferred impurity dopants for use inrendering the GaAlAs layers conducting is silicon at a fluence of 5×10¹³/cm² at 250 KeV followed by Ge at a fluence of 1×10¹³ /cm² at 100 KeV.The donor impurities are shown by cross hatchings in FIG. 2. The choiceof materials for the heteroepitaxial layer 28 is contingent upon forminga lattice match with the active channel material. I the embodiment ofFIG. 2 Gallium Aluminum Arsinide was used. The nominal thickness ofheteroepitaxial layer 28 is 6 to 30 nanometers.

The source 40 and the drain contacts 42 are conventional and may befabricated by any known technique.

The gate control contact 44 may take a variety of forms and may befabricated of a variety of materials. In FIG. 2 it is convenientlyfabricated of titanium tungsten metal in a mushroom configuration.

Referring now to FIG. 3, operating characteristics of the embodiment ofFIG. 2 are discussed.

In operation a negative potential applied to the metal gate contact 44creates a depletion region 50 that acts like an insulating region andrestricts the opening 27 of the active channel 26 available for currentflow. The width of the depletion region 50 depends on the appliedvoltages V_(g) and V_(D). At zero applied gate voltage the depletionregion 50 appears as shown in FIG. 3. When the depth of the deletionregion 50 is large the resistance to current flow is increased.

The current flowing into the drain 42 follows the equation

    I.sub.D =Zqnv.sub.D b,                                     (1)

where Z is the width of the active channel 26, q is the charge of anelectron 1.60218×10⁻¹⁹ coloumb), n is the doping density within theactive channel 26, V_(D) is the applied drain voltage, and b is theheight of the channel opening at the depletion region.

The voltage along the channel increases from zero at the source 40 toV_(D) at the drain 42. Thus the electric field under gate contact 44becomes increasingly higher and the depletion region 50 becomes wider aswe proceed from source 40 to drain 42. The resulting decrease in channelopening must be compensated by an increase in electron velocity tomaintain a constant current through the channel. As V_(D) is increasedfurther, the electrons reach the saturation velocity at the drain end ofthe gate 52. The channel is constricted to the smallest cross sectionb_(o) under the drain end of gate 44, the electric field reaches thecritical value at this point, and I_(D) 54 starts to saturate asillustrated in FIG. 4.

If the drain voltage is increased beyond V_(D) sat, the depletion regionwidens toward the drain 42. This action results in a positive slope ofthe I_(D) -V_(D) and a finite drain resistance beyond currentsaturation.

When a negative voltage is applied to the gate in FIG. 3, the depletionwidth becomes larger. For small V_(D), the channel acts as a linearresistor with large resistance due to narrower channel opening. As V_(D)increases, the critical field is reached at a drain current I_(D) 56lower than in the V_(g) =0 case due to the larger channel resistance.For a further increase in V_(D), the current I_(D) 56 remains saturated.

In the traditional MESFET of FIG. 1 the electrons flow from the sourceto the drain and the initial doping sets the electron carrier density.If the gate 16 is driven positive the electrons will be increasinglyattracted into the gate contact 16 thus decreasing the current flow tothe drain 18. As the gate 16 becomes increasingly positive all theelectrons eventually will be attracted into the gate 16.

Due to the conduction-band-offset, electrons from the heteroepitaxiallayer 28, FIG. 3, are injected into the lower bandgap active channel 26.The injected electrons have more energy than the electrons initiallywithin the active channel 26. The injected electrons are commonlyreferred to as hot. In the present device the additional electronsinjected into the channel 26 by virtue of the heteroepitaxial layer 28increase the charge carrier density beyond the initial doping value.This increased current carrying capability in conjunction with therestricted channel opening allows an increased electric field on thecritical drain edge of the gate 52. The increased electric field permitsan increased drain saturation value according to equation 1. Also, asthe middle region 36 of heteroepitaxial layer 28 is a semi-insulator, itpermits the control gate 44 to be driven somewhat more positive withoutincurring the penalty of drawing excessive gate current. Due to the hotcarrier injection and increased positive gate bias, far more electronsthan the initial doping-density-limited number are flowing in thechannel. Since the gallium aluminum arsenide sections 32,34 beneath thesource 40 and drain 42 contacts are heavily doped, there is a readysource of carriers injected into the active channel 26. Accordingly, thecarrier density of the electrons increases rather than being limited tothe initial doping. Increases have been measured up to 5×10¹⁸ /cm³. Thisoperation mode is referred to as the accumulation mode. The electronsare accumulated to a density greater than the background doping of theactive channel. This increases the maximum current I_(D) 5 to 6 timesthe value possible in conventional MESFETs.

The heteroepitaxial layer 28 may be deposited in any known mannerincluding the techniques of molecular beam epitaxy (MBE) or by metalOxide Chemical Vapor Deposition (MOCVD).

FIG. 5 shows a second embodiment of Transistor 22 wherein theheteroepitaxial layer 28 may be initially impurity doped with vanadiumor Chromium 58, not to exceed a level of 5×10¹⁵ /cm³, which furtherimproves the insulating qualities of the layer 28. When donor impuritiesare added to GaAlAs they thermalize to the conduction band making thesemiconductor a better conductor. However certain types of impuritieswhose energy levels in gallium aluminum arsenide are deep, (i.e., energylevel midway between conduction and valance band) for example vanadiumand chromium, they become trapped (cannot thermalize) and thefermi-level is pinned at mid band gap. Their energy is such that at roomtemperatures they cannot ionize and thermalize into the conduction band.The residual background donors density in the gallium aluminum arsenideis less than that of the implanted vanadium or chromium 58 and are thuscompensated and not available for current conduction. Since breakdownbetween gate and drain typically occurs on the surface of the MESFETsemiconductor 10, FIG. 1, the presence on the surface of insulatingregion 36 of QAMFET 22, FIG. 2, serves to significantly increasebreakdown voltage.

As certain regions 32,34 of the GaAlAs layer 28 now contain donorimpurities whose energy levels exceed those of the underlying GaAs 26conduction band edge and whose concentration density exceeds that of thevanadium, hot carriers are injected into the GaAs channel withoutincurring the penality of additional ionized impurity scattering withinthe channel. As such, the sheet current density within the activechannel 26 increases without decreasing channel mobility thereby leadingto increased transconductance and device gain. This aspect is, however,somewhat offset (at gate voltage below zero) by the electric field dropacross the GaAlAs semi-insulating layer 28. Gain at higher drive levels,however, substantially exceeds that of a MESFET. Additionally, becauseof its higher impurity doping in conjunction with its underlying activechannel, the GaAlAs layer 28 prevents surface states from self depletingthe active GaAs channel 26. In prior art gallium arsenide active channelMESFETs devices 10 of FIG. 1, a metal gate 16, a source contact 14 and adrain contact 18 would be placed directly on the channel layer 12. Thisleaves open sections 15,17 of the channel layer 12 exposed to thesurrounding air. The gallium and arsenide atoms exposed to the aircannot form proper covalent bonds. The bonding that takes place has animproper lattice spacing forming a monolayer near the surface of thechannel layer 12 with a fixed negative surface charges. These surfacecharges are detrimental because they repel electrons in the activechannel. In essence they form depletion regions. In prior art GaAsMESFETs this problem is countered by forming a recessed gate well. Thenthe negative charges at the surface do not deplete down to the depth ofthe channel opening. By covering the active channel layer 26 of thepresent device with the gallium aluminum arsenide, fewer fixed chargesare formed at the surface and depletion of the underlying channel 26 isminimized.

FIG. 6 show a third embodiment of invention wherein heavily (e.g.,2×10¹⁸ /cm³) donor doped GaAs heteroepitaxial layers 60, 62 aredeposited over the first and second regions 32, 34 of the firstheteroepitaxial layer 28 before deposition of the source and draincontacts 40, 42. Layers 60, 62 further improve overall transistorperformance by additionally reducing contact resistance. Each layer 60,62 is approximately 30 nanometers in thickness.

The present Transistor device 22, FIG. 2, has significantly improveddevice efficiency and improved linearity (reduced intermodulationproduct distortion) at any given frequency.

Shown in FIG. 7, is a conventional MESFET drain current/gate voltagecharacteristic compared with the characteristic of thequasi-accumulation mode field effect transistor (QAMFET) of the presentinvention. As the gate is driven positive in a conventional MESFET curve66, the output current saturates. In the QAMFET curve 68, under similardrive, the device automatically converts from depletion mode operationto accumulation mode operation and increases its output current by afactor of up to 5 before saturating. FIG. 8 illustrates thisrelationship as a function of input power and output power. Where theinput/output relationship becomes nonlinear, the output power begins tosaturate and unwanted harmonics and intermodulation product signalsappear. It is seen that a much larger dynamic range of signal handlingcapability is possible with the QAMFET 72 than with the MESFET 70 beforesaturation appears.

Obviously many modifications and variations of the present invention arepossible in light of the above teachings. It is therefore to beunderstood that within the scope of the appended claims the inventionmay be practiced otherwise than as specifically described.

What is claimed and desired to be secured by Letters Patent of theUnited States is:
 1. A quasi accumulation mode field effect transistor,comprising:a semi-insulating substrate layer; an active channel layer ofdoped n-type semi-conductor material disposed on said semi-insulatingsubstrate layer, said channel layer being about 120 nanometers thick andpurposely doped to a concentration of not less than 1×10¹⁷ impurityatoms per cubic centimeter; a first heteroepitaxial semi-insulatinglayer of a semiconductor material disposed on said active channel layer,said first heteroepitaxial layer material having a bandgap greater thanthe bandgap of the active channel layer material, said firstheteroepitaxial layer having a top surface, a designated first region, adesignated second region, and a middle region therebetween, wherein thefirst region and the second region of said first heteroepitaxial layerare implanted with donor impurities and activated; a source contactdisposed on the top surface of the first heteroepitaxial layer on saidfirst region; a drain contact disposed on the top surface of the firstheteroepitaxial layer on said second region; and a gate control contactdisposed on the first heteroepitaxial layer on the middle sectionbetween the source contact and the drain contact, said gate controlcontact being physically separated from the source and drain contacts.2. The quasi accumulation mode field effect transistor of claim 1wherein said first heteroepitaxial layer is n+ in the regions beneathsource and drain contacts.
 3. A method of forming a quasi accumulationmode field effect transistor, comprising the steps of:providing asemi-insulating substrate layer; disposing an active channel layer ofdoped n-type semi-conductor material on said semi-insulating substratelayer; disposing a first heteroepitaxial semi-insulating layer of asemi-conductor material on said active channel layer, said firstheteroepitaxial layer material having a bandgap greater than the bandgapof the active channel layer material, said first heteroepitaxial layerhaving a top surface, a designated first region, a designated secondregion, and a middle region therebetween wherein the first region andthe second region of said first heteroepitaxial layer are implanted withdonor impurities and activated; disposing a source contact on the topsurface of the first heteroepitaxial layer above said first region;disposing a drain contact on the top surface of the firstheteroepitaxial layer above said second region; and disposing a gatecontrol contact on the first heteroepitaxial layer, said gate controlcontact positioned on the middle section between the source contact andthe drain contact, said gate control contact being physically separatedfrom the source and drain contacts.
 4. The method of forming a quasiaccumulation mode field effect transistor as recited in claim 3, furthercomprising the steps of:disposing a layer of n+doped semi-conductormaterial between the source contact and the first heteroepitaxial layer;and disposing a layer of n+doped semi-conductor material between thedrain contact and the first heteroepitaxial layer; wherein said n+dopedsemi-conductor material layers form second and third heteroepitaxiallayers.
 5. The method of forming a quasi accumulation mode field effecttransistor as recited in claim 3 further comprising the stepof:implanting said first heteroepitaxial layer with activated n+donorimpurities to form an n+ first heteroepitaxial layer.
 6. A quasiaccumulation mode field effect transistor, comprising:a gallium arsenidesubstrate layer; an active channel layer of doped n-type galliumarsenide disposed on said gallium arsenide substrate layer, said channellayer being about 120 nanometers thick and purposely doped to aconcentration of not less than 1×10¹⁷ impurity atoms per cubiccentimeter; a first heteroepitaxial semi-insulating layer of galliumaluminum arsenide disposed on said active channel layer, said firstheteroepitiaxial layer material having a bandgap greater than thebandgap of the active channel layer material, said first heteroepitaxiallayer having a top surface, a designated first region, a designatedsecond region, and a middle region therebetween, wherein the firstregion and the second region of said first heteroepitaxial layer areimplanted with donor impurities and activated; a source contact disposedon the top surface of the first heteroepitaxial layer above said firstregion; a drain contact disposed on the top surface of the firstheteroepitaxial layer above said second region; and a gate controlcontact disposed on the first heteroepitaxial layer, said gate controlcontact positioned on the middle section between the source contact andthe drain contact, said gate control contact being physically separatedfrom the source and drain contacts.
 7. The quasi accumulation mode fieldeffect transistor of claim 6 wherein said heteroepitaxial layer containsVanadium as impurity in concentration not to exceed 5×10¹⁵ per cubiccentimeter.
 8. A quasi accumulation mode field effect transistor,comprising:a semi-insulating substrate layer; an active channel layer ofdoped n-type semiconductor material disposed on said semi-insulatingsubstrate layer, said channel layer being about 120 nanometers thick andpurposely doped to a concentration of not less than 1×10¹⁷ impurityatoms per cubic centimeter; a first heteroepitaxial semi-insulatinglayer of a semiconductor material disposed on said active channel layer,said first heteroepitaxial layer material having a bandgap greater thanthe bandgap of the active channel layer material, said firstheteroepitaxial layer having a top surface, a designated first region, adesignated second region, and a middle region therebetween, wherein thefirst region and the second region of said first heteroepitaxial layerare implanted with donor impurities and activated; a layer of n+ dopedsemiconductor material positioned on said first region of said firstheteroepitaxial layer; a source contact disposed on the top surface ofthe layer of n+ doped semi-conductor material; another layer of n+ dopedsemiconductor material positioned on said second region of said firstepitaxial layer; a drain contact disposed on the top surface of saidanother layer of n+ doped semiconductor material; and a gate controlcontact disposed on said middle region of the first heteroepitaxiallayer between the source contact and the drain contact, said gatecontact being physically separated from the source and drain contacts.9. A quasi accumulation mode field effect transistor, comprising:asemi-insulating substrate layer; an active channel layer of doped n-typesemiconductor material disposed on said semi-insulating substrate layer,said channel region being about 120 nonometers thick and purposely dopedto a concentration of not less than 1×10¹⁷ impurity atoms per cubiccentimeter; a first heteroepitaxial semi-insulating layer of asemiconductor material disposed on said active channel layer, said firstheteroepitaxial layer material having a bandgap greater than the bandgapof the active channel layer material, said first heteroepitaxial layerhaving a top surface, a designated first region, a designated secondregion, and a middle region therebetween, wherein the first region andthe second region of said first heteroepitaxial layer are implanted withdonor impurities and activated; a layer of n+ doped semiconductormaterial positioned on said first region of said first heteroepitaxiallayer; a source contact disposed on the top surface of said layer of n+doped semiconductor material; another layer of n+ doped semiconductormaterial positioned on said second region of said first heteroepitaxiallayer; a drain contact disposed on the top surface of said another layerof n+ doped semiconductor material; and a gate control contact disposedon the first heteroepitaxial layer, said gate control contact positionedon the middle section between the source contact and the drain contact,said gate control contact being physically separated from the source anddrain contacts.